Platform Validation Engineer is responsible for validating the industry leading SOC implementation tools and flow solution, like “IC Compiler II”, “Design Complier”, Formality and next generation Digital platform “Fusion Complier” etc.
· Understand Customer request, Base on Digital design flow to verify new features, Include new features under advanced node, 5nm and 3nm etc.
· Validate Synopsys Frontend/Backend flow, keep to trace Frontend/Backend flow QOR/Performance.
· Understand customer usage, propose new request, to enhance flow solution.
· Design and develop test programs in Perl, TCL, Python, or C/C++, including test tools and automated test suites.
· MS in EE, Microelectronics or relevant with three years’ experience（欢迎2021应届毕业生）
· Be proficient in ASIC design flow. Include Floorplan, Synthesis, P&R, STA, etc. Expected to identify classical solutions to problems under little review and guidance
· Team-worker and great learner, Keep passion and interest to advanced technology and design flow methodology!
· Must have good verbal and written communication skills for both Chinese and English
· Knowledge and experience in one or more of the following CS fields is a strong plus:
Job Descriptions
This position is responsible for IP FPGA prototype work including IP core RTL integration, UVM verification, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.
Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the IP FPGA prototype integration architecture and test plan
Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve good synthesis result
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification.
Position Requirements
BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation.
Must be proficient with Unix OS, Verilog HDL, Shell scripting.
Hardware validation and debugging or IP or ASIC design UVM verification skill or experiences are highly desirable.
Knowledge one of the PCIe/USB/AMBA Protocol or relevant high-speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus.
Be very familiar with Xilinx FPGA Synthesis, Place, Route, have successful experience in solving timing violation
Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills
Interface IP Application Engineer
Location：shanghai/Beijing/Shenzhen
职能：集成电路IC设计/应用工程师
薪资：30-40万
Synopsys offers a broad portfolio of high-quality, silicon-proven IP solutions for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. This position will be responsible for technical support of customers using Synopsys DesignWare Cores IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. Responsibilities Include
- Discussing with customer on their application and SoC design, Capturing and understanding their design requirements, Proposing DW IP solutions to best-fit customer requirements with competitive PPA
- Providing direct technical support and assistance to enable customers to use DW IP successfully
- Working with the sales teams to manage the IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships
- Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across the business units and with other product line teams to provide high quality support for customers.
- Writing application notes, attend technical conferences and review projects and protocol specifications.
- Providing technical guidance and support to the sales team during calls, meetings, and marketing events.
Requirements:
- Bachelors and/or Master’s Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science.
- Experience with one or more I/O protocols, such as Ethernet, USB, DDR, HBM2, PCIe, CCIX, MIPI, SATA, HDMI, Mobile Storage and Multi-protocol Serdes are preferred.
- An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred.
- Minimum of 5 years relevant experience in ASIC/SoC front-end design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking.
- Full understanding of digital design methodologies and tools including formal verification.
- Ideally have experienced at least one ASIC/SoC tape-out from concept to full production.
- Silicon debug and troubleshooting skills are highly desirable.
- Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities.
- Strong communication skills and ability to interact with customers as well as peers.
- High degree of self-motivation and personal responsibility.
- Strong analytical, reasoning and problem solving skills and attention to details
Software Engineer (AI Lab)
Location：shanghai/Beijing
职能：集成电路IC设计/应用工程师
薪资：20-35万
Job Descriptions
1. Developing and maintaining the software platform, toolchains, and libraries for design, analyze and validation AI hardware.
2. Working with compiler engineers to develop and maintain the infrastructure of compiler.
3. Collaborates hardware engineers for proof of concept, demonstration, and performance evaluation
Minimum Requirements
1. MS CS/EE/Applied math or relevant or BS with 2+ years of industrial experience
2. Familiar with modern C++ development
3. Familiar with python development
4. Good knowledge of data structure and algorithm, algorithm optimization
5. Basic knowledge of software development toolchain for Linux, such as gcc, gdb
6. Basic knowledge of software engine concept
7. Basic knowledge of software designing
Preferred Qualifications
1. Familiar with git, cmake and other development tools
2. Strong written and verbal communication skills
3. Basic Knowledge of machine learning, deep learning, and other AI algorithms
4. Familiar with deep learning frameworks, such as Caffe/Tensorflow
5. Experience in compiler development such as llvm, tvm is a good plus
6. Experience in EDA tools development is a good plus
7. Experience in AI accelerator toolchains is a good plus
8. Experience on CI/CD system development is a good plus
模拟混合信号设计工程师
薪资：13-25万
职能：集成电路IC设计
Location：Wuhan
基本要求：
-电子工程或相关专业本科学历
Bachelor in EE and related fields
-具有信号与系统、数字/模拟电路、半导体物理、数字/模拟集成电路设计等相关专业课程基础。
Basic knowledge of signal and system, digital/analog circuits, semiconductor physics, digital/analog integrated circuit design, etc.
-至少具有两项以下专业能力：
1、至少对以下电路模块中的某一项有深入了解或设计经验：OTA, Comparator, Bandgaps, OSC, DC-DC/LDO, Transmitters, Receivers, ADC/DAC, PLL, Clock and Data Recovery…
Knowledgeable or experienced in at least one of following circuit blocks : OTA, Comparator, Bandgaps, OSC, DC-DC/LDO, Transmitters, Receivers, ADC/DAC, PLL, Clock and Data Recovery…
2、会使用电路设计工具，版图设计工具以及SPICE仿真工具
Familiar with tools for schematic entry, IC layout and SPICE simulation
3、对集成电路版图有一定的了解，或拥有相关经验
Understood or experienced in integrated circuit layout
4、会使用Verilog-A语言对模拟电路进行行为级建模和仿真
Familiar with Verilog-A for analog behavioral modeling and simulation-control/data-capture
5、熟悉TCL，Perl，C，Python，MATLAB或其他脚本语言
Familiar with TCL, perl, C, python, MATLAB, or other scripting languages
6、具有较强的学习能力
Learning ability
-有一定的英语听说写能力
Writing and reading English can meet basic daily working requirements
-有良好的人际交流与团队合作能力
Good interpersonal communication and teamwork skills
岗位关键词：
- 使用最先进的工艺（如5nm/7nm）开发创新型模拟与混合集成电路
Design innovative analog and mixed-signal integrated circuits based on advanced technology (like 5nm/7nm)
- 与全球具有不同技术背景的模拟/数字电路设计工程师协同工作
Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds
- 从事与模拟混合信号相关的IP设计
involve related to analog design and mixed signal IP design
- 基于CMOS器件的电路设计，开发混合信号IP
Circuit Design based on CMOS device and develop analog and mixed signal I
版图设计工程师
薪资：13-25万
职能：集成电路IC设计
Location: Wuhan
- 学士及学士以上学历 （微电子，电子信息，或者自动化专业优先考虑）
Bachelor or above degree in Microelectronics, electronics, automation related major is preferred
- 有版图设计经验优先考虑
Layout relevant project experience is prior
- 英文通过四级，有一定听说写能力
Language proficiency over level 4 and listening, writing and reading can meet basic daily working requirements
- 良好的合作和沟通能力
Good team player and skillful communication
岗位关键词：
- 使用先进工艺（如7nm/10nm）根据电路设计完成版图设计。验证版图设计的DRC/LVS，确保版图设计正确性
According schematic to custom design layout with advanced process node (Like 7nm/10nm), verify layout design with DRC/LVS deck
- 与全球具有不同技术背景工程师协同工作
Work with a cross functional design team from a wide variety of backgrounds
2021校招-数字电路设计/验证工程师
职能：集成电路IC设计/数字前端
薪资:12-36万
Location: Wuhan/shanghai
基本要求
- 微电子、电子工程、通信或相关专业研究生
Typically requires fresh master/PHD graduate with the major of microelectronics, telecommunication,
Electrical/Electronic Engineering, or relevance
- 熟悉数字设计的基本流程，熟练使用Verilog语言对数字电路进行设计或SystemVerilog进行验证
Familiar with basic digital design flow, experience with Verilog language for digital design or SystemVerilog
for verification
- 有使用过脚本语言，如TCL, Perl, Python等
Experience with TCL, Perl, Python, or other scripting languages
岗位关键词
- 从事的相关产品是接口控制器 (Interface controller) / 高速DDR PHY /静态存储器/处理器 (Processor) 等
The related products are Interface controller, High Speed DDR PHY, Static memory，Processor etc.
- 使用先进设计工艺（如5nm/7nm/10nm），从事数字设计，UVM验证，以及业内领先的开发流程相关
工作，如Timing，DFT, Firmware等相关工作
Work on Digital Design, UVM Verification, and state-of-the-art implementation flow development
including Timing, DFT and Firmware tasks with advanced technology (5nm/7nm/10nm). Work on Digital Design, UVM Verification, and state-of-the-art implementation flow development
including Timing, DFT and Firmware tasks with advanced technology (5nm/7nm/10nm).